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ADE7953
Data Sheet
ADE7953 REGISTERS
The ADE7953 contains registers that are 8, 16, 24, and 32 bits long. All signed registers are in the twos complement format with the
exception of the PHCALA and PHCALB registers, which are in sign magnitude format. The 24-bit and 32-bit registers contain the same
data but can be accessed in two different register lengths. The 24-bit register option increases communication speed; the 32-bit register
option provides simplicity when coding with the long format. When accessing the 32-bit registers, only the lower 24 bits contain valid
data (the upper 8 bits are sign extended). A write to a 24-bit register changes the value in the corresponding 32-bit register, and vice versa.
Therefore, each 24-bit/32-bit register can be thought of as one memory location that can be accessed via two different paths.
Table 13. 8-Bit Registers
Address
0x000
0x001
0x004
0x007
0x008
0x009
0x040
0x0FD
Register Name
SAGCYC
DISNOLOAD
LCYCMODE
PGA_V
PGA_IA
PGA_IB
WRITE_PROTECT
LAST_OP
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Default
0x00
0x00
0x40
0x00
0x00
0x00
0x00
0x00
Type
Unsigned
Unsigned
Unsigned
Unsigned
Unsigned
Unsigned
Unsigned
Unsigned
Register Description
Sag line cycles
No-load detection disable (see Table 16)
Line cycle accumulation mode configuration (see Table 17)
Voltage channel gain configuration (Bits[2:0])
Current Channel A gain configuration (Bits[2:0])
Current Channel B gain configuration (Bits[2:0])
Write protection bits (Bits[2:0])
Contains the type (read or write) of the last successful communication (0x35 =
read; 0xCA = write)
0x0FF
0x702
0x800
LAST_RWDATA
Version
EX_REF
R
R
R/W
0x00
N/A
0x00
Unsigned
Unsigned
Unsigned
Contains the data from the last successful 8-bit register communication
Contains the silicon version number
Reference input configuration: set to 0 for internal; set to 1 for external
Table 14. 16-Bit Registers
Address
0x100
0x101
0x102
0x103
Register Name
ZXTOUT
LINECYC
CONFIG
CF1DEN
R/W
R/W
R/W
R/W
R/W
Default
0xFFFF
0x0000
0x8004
0x003F
Type
Unsigned
Unsigned
Unsigned
Unsigned
Register Description
Zero-crossing timeout
Number of half line cycles for line cycle energy accumulation mode
Configuration register (see Table 18)
CF1 frequency divider denominator. When modifying this register, two
sequential write operations must be performed to ensure that the write is
successful.
0x104
CF2DEN
R/W
0x003F
Unsigned
CF2 frequency divider denominator. When modifying this register, two
sequential write operations must be performed to ensure that the write is
successful.
0x107
0x108
CFMODE
PHCALA
R/W
R/W
0x0300
0x0000
Unsigned
Signed
CF output selection (see Table 19)
Phase calibration register (Current Channel A). This register is in sign
magnitude format.
0x109
PHCALB
R/W
0x0000
Signed
Phase calibration register (Current Channel B). This register is in sign
magnitude format.
0x10A
0x10B
0x10C
0x10D
0x10E
0x110
0x1FE
0x1FF
0x120
PFA
PFB
ANGLE_A
ANGLE_B
Period
ALT_OUTPUT
LAST_ADD
LAST_RWDATA
Reserved
R
R
R
R
R
R/W
R
R
R/W
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
Signed
Signed
Signed
Signed
Unsigned
Unsigned
Unsigned
Unsigned
Unsigned
Power factor (Current Channel A)
Power factor (Current Channel B)
Angle between the voltage input and the Current Channel A input
Angle between the voltage input and the Current Channel B input
Period register
Alternative output functions (see Table 20)
Contains the address of the last successful communication
Contains the data from the last successful 16-bit register communication
This register should be set to 30h to meet the performance specified in
Table 1. To modify this register, it must be unlocked by setting Register
Address 0xFE to 0xAD immediately prior.
Rev. B | Page 60 of 72
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